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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
High Performance low spurious operation
The HMC703LP4E has been designed for the best phase noise and low spurious content possible in an integrated
synthesizer. spurious signals in a synthesizer can occur in any mode of operation and can come from a number of
sources.
figure of Merit, noise floor, and flicker noise Models
The phase noise of an ideal phase locked oscillator is dependent upon a number of factors:
a. Frequency of the VCO, and the Phase detector
b. VCO sensitivity, kvco, VCO and Reference Oscillator phase noise profiles
c. Charge Pump current, Loop Filter and Loop Bandwidth
d. Mode of Operation: Integer, Fractional modulator style
The contributions of the PLL to the output phase noise can be characterized in terms of a Figure of Merit (FOM) for both
the PLL noise floor and the PLL flicker (1/f) noise regions, as follows:
where:
Ф
p
2
Phase Noise Contribution of the PLL (rads2/Hz)
fo
Frequency of the VCO (Hz)
fpd
Frequency of the Phase Detector (Hz)
fm
Frequency offset from the carrier (Hz)
Fpo
Figure of Merit (FOM) for the phase noise floor
Fp1
Figure of Merit (FOM) for the flicker noise region
Figure 27. Figure of Merit Noise Models for the PLL
If the free running phase noise of the VCO is known, it may also be represented by a figure of merit for both 1/f2 , Fv2,
and the 1/f3, Fv3, regions.
(
)
2
0
2
0
1
0,,
p
m pd
m
pd
Ff
ff f
ff
=
+
PLL Phase Noise
Contribution
(eQ 1)
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